The present invention is drawn to a new method of bumping a semiconductor device (either a singulated die or a plurality of die in wafer form) and attaching a semiconductor die to a substrate. Alternatively stated, the present invention is drawn to chip-to-package interconnections or first-level packaging interconnections for packaging semiconductor die.
Several techniques have been utilized in the prior art to execute chip-to-package interconnections. Conventional techniques include wire bonding and tape automated bonding. However, as is well known in the art, such prior art techniques suffer from numerous disadvantages. For example, wire bonding is not particularly adapted for a high density of I/O interconnects between the substrate and the semiconductor die, and has an undesirably high inductance due to the long electrical connection path of wires. In addition, wire bonding is relatively expensive, unreliable and has relatively low productivity due to the manual wire bonding to make interconnection between the semiconductor die and the substrate.
In an attempt to attend to the deficiencies of prior art wire bonding techniques, the so-called Controlled Collapse Chip Connection technology was developed, alternatively referred to in the art as "C4" or "flip-chip" technology. As is known in the art, in flip-chip processing, a semiconductor device, typically a plurality of semiconductor die still in wafer form, is provided having an active surface on which active regions are provided. A contact is provided on the active surface, the contact making electrical connection with an active region. A bumping site is then provided on the contact, referred to in the art as an under-bump metallization (UBM). Numerous of such contacts and sites are provided on the active surface of a semiconductor device, such as 100-1,000 sites per die, typically around 400 per die. The bumping sites are generally composed of a Cr adhesive layer, a Cu solderable layer formed on the Cr layer, and an Au flash layer provided to prevent oxidation of the Cu solderable layer. Thereafter, an Mo mask is positioned over the semiconductor die, the mask having openings corresponding to the bumping sites. Then, Pb and Sn are co-deposited, on the mask and through the mask openings so as to deposit on the individual bumping sites. Thereafter, the die is heated so as to reflow the Pb/Sn material deposited on the bumping sites to form solder bumps. After reflow, the semiconductor die is flipped (i.e., active surface facing downward) and placed on a substrate having complementary lands, which align with the bumps formed on the semiconductor die. A second reflow step is carried out to execute physical and electrical connection between the die (after singulation) and the substrate via the solder bumps which form solder joints.
While flip-chip technology has been widely used in the industry to provide small packages having a high density of I/O interconnections, the flip-chip technique still suffers from several disadvantages. For example, flip-chip technology is relatively expensive, takes several hours to complete (e.g., long cycle time), and requires a custom Mo mask. Due to the use of the mask, a great deal of material (Pb and Sn) is wasted, since the material deposits on the mask (i.e., does not preferentially deposit on the bumping sites exposed through the openings in the mask). Further, the mask is relatively expensive, and cannot be reused more than a few times due to the deposition of the Pb and Sn thereon, even if the mask is cleaned between deposition steps. Further, the thermal expansion mismatch between the semiconductor wafer and the Mo mask prevents use of larger masks for today's large-sized semiconductor wafers. Furthermore, flip-chip technology requires two separate reflows, a first reflow after Pb/Sn deposition to form a solder bump and ensure attachment of the bump to the bumping site of the semiconductor device, and a second reflow to execute electrical and mechanical connection between the semiconductor die and the substrate.
In conjunction with conventional flip-chip processing, use of solder balls has been considered to form landing pads on the substrate to which the bumped semiconductor die is attached, by placing solder balls on a substrate, reflowing and planarizing same. However, this technique still requires the use of conventional flip-chip processing, and suffers from the disadvantages associated therewith.
Accordingly, a need continues to exist in the art for an improved chip-to-package interconnection technique that overcomes the disadvantages associated with manual wire bonding and flip-chip techniques.